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International Journal of Engineering، جلد ۲۶، شماره ۳، صفحات ۳۱۵-۳۲۲
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| عنوان فارسی |
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| چکیده فارسی مقاله |
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| کلیدواژه‌های فارسی مقاله |
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| عنوان انگلیسی |
High-performance and Low-power Clock Branch Sharing Pseudo-NMOS Level Converting Flip-flop |
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| چکیده انگلیسی مقاله |
Multi-Supply voltage design using Cluster Voltage Scaling (CVS) is an effective way to reduce power consumption without performance degradation. One of the major issues in this method is performance and power overheads due to insertion of Level Converting Flip-Flops (LCFF) at the interface from low-supply to high-supply clusters to simultaneously perform latching and level conversion. In this paper, an improved version of clocked pseudo-NMOS LCFF called Clock Branch Sharing pseudo-NMOS LCFF has been proposed, which combines the Conditional Discharge technique, pseudo-NMOS technique and Clock Branch Sharing technique. Based on Simulation results, the proposed flip-flop exhibits up to 32.5% delay reduction and saves power up to 8.1% as compared to clocked pseudo-NMOS LCFF. |
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| کلیدواژه‌های انگلیسی مقاله |
low power, Level Conversion, Flip, Flops, multi, VDD Systems |
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| نویسندگان مقاله |
Yateesh Sharma |
Electronics & Communications Engineering, National Institute of Technology Kurukhshetra
N.P. Singh |
Electronics & Communications Engineering, National Institute of Technology Kurukhshetra
Kapil Juneja |
Electronics & Communications Engineering, National Institute of Technology Kurukhshetra
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| نشانی اینترنتی |
http://www.ije.ir/article_72100_f68b17db1e1d2a08ebfdb1cec56a1d64.pdf |
| فایل مقاله |
اشکال در دسترسی به فایل - ./files/site1/rds_journals/409/article-409-2062945.pdf |
| کد مقاله (doi) |
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| زبان مقاله منتشر شده |
en |
| موضوعات مقاله منتشر شده |
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| نوع مقاله منتشر شده |
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